The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method of filling, e.g., an element isolation trench or a recess portion for an interconnection or between electrodes with an insulating film.
In a semiconductor device, to electrically isolate elements formed on a substrate, element isolation is used, in which a trench is formed between elements in a surface region of a substrate and filled with an insulating film. This method is called shallow trench isolation (to be referred to as STI hereinafter).
In addition, portions between interconnection layers or between electrodes formed on the substrate as a conductive film pattern must be filled with an interlayer dielectric film.
To fill these recess portions with an insulating film, a silicon oxide film is formed by high density plasma chemical vapor deposition (to be referred to as HDP-CVD hereinafter) or by thermal CVD using TEOS/O3 gas.
However, along with the recent progress in micropatterning of devices, the aspect ratios of recess portions are becoming high. Hence, it is very difficult to fill recess portions without generating any void or seam.
FIGS. 15A to 15H show steps in filling element isolation trenches by a conventional method. As shown in FIG. 15A, a silicon oxide film 1102 is formed on the surface of a semiconductor substrate 1101 by thermal oxidation.
As shown in FIG. 15B, a silicon nitride film 1103 is deposited on the resultant structure. This silicon nitride film 1103 is patterned to obtain a mask for trench formation.
As shown in FIG. 15C, the semiconductor substrate 1101 is etched by, e.g., RIE (Reactive Ion Etching) using the silicon nitride film 1103 as a mask, thereby forming trenches 1105. A silicon oxide film 1104 is formed on the side walls and bottom surfaces of the trenches 1105 by thermal oxidation.
As shown in FIG. 15D, a silicon oxide film 1106 is deposited by HDP-CVD to fill the trenches 1105. In this process of depositing the silicon oxide film 1106, overhangs 1107 are formed. When the silicon oxide film 1106 is further deposited, voids 1108 are formed, as shown in FIG. 15E.
As shown in FIG. 15F, the surface is planarized by CMP (Chemical Mechanical Polishing). The planarization processing is stopped at the silicon nitride film 1103 serving as a stopper.
As shown in FIG. 15G, the silicon nitride film 1103 is removed by etching.
As shown in FIG. 15H, the silicon oxide film 1106 that projects from the surface of the semiconductor substrate 1101 is removed by etching.
Portions (seams) 1109 where the influence of the voids 1108 remains are present on the surface of the resultant silicon oxide film 1106, as shown in FIG. 15H.
As another method of forming a silicon oxide film, Spin On Glass (to be referred to as SOG hereinafter) using a liquid source can also be used. According to this method, the material of a silicon oxide film is melted into a solvent. A forming portion is coated with the liquid, and then, annealing is executed, thereby forming a silicon oxide film.
In this method, however, the film shrinks. When a trench is filled with the film, large stress may occur, or the film may peeled from the inner wall of the trench. Additionally, even when annealing is executed for a film buried in a trench, the film cannot be sufficiently sintered, and an impurity remains in the film. As a consequence, the quality of the resultant film is not satisfactory. This may affect the element isolation resistance or isolation resistance between interconnection layers or between electrodes.
As described above, it is conventionally difficult to fill a trench or a recess portion between interconnection layers or between electrodes with an insulating material while ensuring sufficient electrical isolation resistance without generating any void or seam.